View IDT7M1002_430109.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7M1002
FEATURES
* High-density 512K CMOS Dual-Port RAM module * Fast access times --Commercial: 30, 35ns --Military: 40, 45ns * Fully asynchronous read/write operation from either port * Easy to expand data bus width to 64 bits or more using the Master/Slave function * Separate byte read/write signals for byte control * On-chip port arbitration logic * INT flag for port-to-port communication * Full on-chip hardware support of semaphore signaling between ports * Surface mounted fine pitch (25 mil) LCC packages allow through-hole module to fit into 121 pin PGA footprint * Single 5V (10%) power supply * Inputs/outputs directly TTL-compatible
DESCRIPTION
The IDT7M1002 is a 16K x 32 high-speed CMOS Dual-Port Static RAM Module constructed on a co-fired ceramic substrate using four 16K x 8 (IDT7006) Dual-Port Static RAMs in surface-mounted LCC packages. The IDT7M1002 module is designed to be used as stand-alone 512K Dual-Port RAM or as a combination Master/Slave Dual-Port RAM for 64-bit or more word width systems. Using the IDT Master/Slave approach in such system applications results in full-speed, errorfree operation without the need for additional discrete logic. The module provides two independent ports with separate control, address, and I/O pins that permit independent and asynchronous access for reads or writes to any location in memory. System performance is enhanced by facilitating port-to-port communication via additional control signals SEM and INT. The IDT7M1002 module is packaged in a ceramic 121 pin PGA (Pin Grid Array)1.35 inches on a side. Maximum access times as fast as 30ns are available over the commercial temperature range and 40ns over the military temperature range. All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest revision of MIL-STD-883, Class B making them ideally suited to applications demanding the highest level of performance and reliability.
PIN CONFIGURATION
1 A B C D E F G H I J K L M L_I/O(24) L_I/O(23) L_I/O(21) L_I/O(19) L_I/O(17) L_SEM L_BUSY L_R/W (1) L_I/O(15) L_I/O(13) L_I/O(11) L_I/O(10) L_I/O(9) 2 L_I/O(26) L_I/O(25) L_I/O(22) L_I/O(20) L_I/O(18) L_I/O(16) L_INT L_R/W(2) L_I/O(14) L_I/O(12) M/S L_I/O(8) L_I/O(7) 3 L_I/O(28) L_I/O(27) VCC L_A(4) L_A(5) L_A(6) GND L_A(7) L_A(8) L_A(9) GND L_I/O(6) L_I/O(5) L_A(10) L_I/O(4) L_I/O(3) L_A(11) L_I/O(2) L_I/O(1) L_A(12) L_A(13) L_I/O(0) GND R_R/W (4) R_R/W (3) R_A(12) R_A(13) R_I/O(0) R_A(11) R_I/O(2) R_I/O(1) R_A(10) R_I/O(4) R_I/O(3) 4 L_I/O(30) L_I/O(29) L_A(3) GND 5 L_CS L_I/O(31) L_A(2) 6 L_OE L_A(0) L_A(1) 7 L_R/W(3) L_R/W(4) GND 8 R_OE R_A(0) R_A(1) 9 R_CS R_I/O(31) R_A(2) 10 R_I/O(30) R_I/O(29) R_A(3) 11 R_I/O(28) R_I/O(27) GND R_A(4) R_A(5) 12 R_I/O(26) R_I/O(25) R_I/O(22) R_I/O(20) R_I/O(18) R_I/O(16) R_INT 13 R_I/O(24) R_I/O(23) R_I/O(21) R_I/O(19) R_I/O(17) R_SEM R_BUSY
PGA TOP VIEW
R_A(6) GND R_A(7) R_A(8) R_A(9) VCC R_I/O(6) R_I/O(5)
R_R/W (2) R_R/W (1) R_I/O(14) R_I/O(12) GND R_I/O(8) R_I/O(7) R_I/O(15) R_I/O(13) R_I/O(11) R_I/O(10) R_I/O(9)
2795 drw 01
The IDT logo is a registered trademark of Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2795/5
7.02
1
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
L_A(0-13) L_I/O(0-7) L_ CS L_ OE L_ SEM L_ INT
M/S R_A(0-13) R_I/O(0-7) IDT7006 16K x 8 (ARBITRATION LOGIC) R_CS R_OE R_SEM R_INT
L_ BUSY L_R/W (0)
R_BUSY R_R/W (0)
L_I/O(8-15) IDT7006 16K x 8 (ARBITRATION LOGIC) L_ R/W (1)
R_I/O(8-15)
R_ R/W (1)
L_I/O(16-23) IDT7006 16K x 8 (ARBITRATION LOGIC) L_ R/W (2)
R_I/O(16-23)
R_R/W (2)
L_I/O(24-31) IDT7006 16K x 8 (ARBITRATION LOGIC) L_R/W (3)
R_I/O(24-31)
R_ R/W (3)
2795 drw 02
PIN NAMES
Left Port L_A (0-13) L_I/O (0-31) L_R/W (1-4) L_CS L_OE L_BUSY L_INT L_SEM M/S VCC GND Right Port R_A (0-13) R_I/O (0-31) R_R/W (1-4) R_CS R_OE R_BUSY R_INT R_SEM Description Address Inputs Data Inputs/Outputs Read/Write Enables Chip Select Output Enable Busy Flag Interrupt Flag Semaphore Control Master/Slave Control Power Ground
2795 tbl 01
7.02
2
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commerical -0.5 to +7.0 Military -0.5 to +7.0 Unit V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2795 tbl 03
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
Military Commercial
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. Unit 5.5 0 6.0 0.8 V V V V
2795 tbl 04
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2795 tbl 02
VCC GND VIH VIL
NOTE: 1. VIL -3.0V for pulse width less than 20ns
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = -55C to +125C or 0C to +70C) Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage (Address & Control) Input Leakage (Data) Output Leakage (Data) Output Low Output High Voltage Test Conditions VCC = Max. VIN = GND to VCC VCC = Max. VIN = GND to VCC VCC = Max. CS VIH, VOUT = GND to VCC VCC = Min. IOL = 4mA Voltage VCC = Min, IOH = -4mA Min. -- -- -- -- 2.4 Max. 40 10 10 0.4 -- Units A A A V V
2795 tbl 05
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = -55C to +125C or 0C to +70C) Commercial Symbol ICC2 ISB ISB1 ISB2 Parameter Dynamic Operating Current (Both Ports Active) Standby Supply Current (Both Ports Inactive) Standby Suppy Current (One Port Inactive) Full Standby Supply Current (Both Ports Inactive) Test Conditions VCC = Max., CS VIL, SEM = Don't Care Outputs Open, f = fMAX VCC = Max., L_CS and R_CS VIH Outputs Open, f = fMAX VCC = Max., L_CS or R_CS VIH Outputs Open, f = fMAX L_CS and R_CS VCC - 0.2V VIN > VCC - 0.2V or < 0.2V L_SEM and R_SEM VCC - 0.2V Min. -- -- -- -- Max. 1360 280 1000 60 Military Min. -- -- -- -- Max. 1600 340 1160 120 Units mA mA mA mA
2795 tbl 06
7.02
3
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE(1) (TA = +25C, f = 1.0MHz)
Symbol Parameter CIN (1) CIN(2) CIN(3) COUT Input Capacitance (CS, OE, SEM, Address) Input Capacitance (R/W, I/O, INT) Input Capacitance (BUSY, M/S) Output Capacitance (I/O) Condition VIN = 0V VIN = 0V VIN = 0V VOUT = 0V Max. Unit 40 12 45 12 pF pF pF pF
*Including scope and jig capacitances. NOTE:
2795 tbl 07
+5V
480 BUSY, INT 255 30pF*
1. This parameter is guaranteed by design but not tested.
Figure 1. Output Load
2795 drw 03
+5V
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2795 tbl 08
480 DATAOUT 255 5pF*
*Including scope and jig capacitances.
2795 drw 04
Figure 2. Output Load
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = -55C to +125C or 0C to +70C)
(For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
7M1002SxxG 30 -35 Symbol Read Cycle tRC tAA tACS(2) tOE tOH tLZ(1) tHZ
(1)
7M1002SxxGB -40 -45 Max. -- 35 35 20 -- -- 15 -- 50 -- -- -- -- -- -- -- Min. 40 -- -- -- 3 3 -- 0 -- 15 40 35 35 0 35 0 Max. -- 40 40 22 -- -- 17 -- 50 -- -- -- -- -- -- -- Min. 45 -- -- -- 3 5 -- 0 -- 15 45 40 40 0 35 0 Max. Unit -- 45 45 25 -- -- 20 -- 50 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2795 tbl 09
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable Access Time Output Hold from Address Change Output to Low-Z Output to High-Z Chip Select to Power Up Time Chip Deselect to Power Up Time Sem. Flag Update Pulse (OE or SEM) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-Up Time Write Pulse Width Write Recovery Time
Min. 30 -- -- -- 3 3 -- 0 -- 15 30 25 25 0 25 0
Max. -- 30 30 17 -- -- 15 -- 50 -- -- -- -- -- -- --
Min. 35 -- -- -- 3 3 -- 0 -- 15 35 30 30 0 30 0
tPU(1) tPD(1) tSOP tWC tCW(2) tAW tAS tWP tWR
Write Cycle
(Continued on next page)
7.02
4
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 55C to +125C or 0C to +70C)
7M1002SxxG 7M1002SxxGB
30 Symbol tDW tDH tHZ
(1)
-35 Max. -- -- 15 -- -- -- Min. 25 0 -- 0 10 10 Max. -- -- 15 -- -- --
-40 Min. 25 0 -- 0 10 10 Max. -- -- 17 -- -- --
-45 Min. 25 0 -- 0 10 10 Max. Unit -- -- 20 -- -- -- ns ns ns ns ns ns
Parameter Data Valid to End-of-Write Data Hold Time Output to High-Z Output Active from End-of-Write
SEM SEM
Min. 22 0 -- 0 10 10
Write Cycle (continued)
tOW(1) tSWRD tSPS
Flag Write to Read Time Flag Contention Window
(3)
Busy Cycle-Master Mode tBAA tBDA tBAC tBDC tWDD tDDD tAPS(6) tBDD tWB(7) tWH
(8) (5) (5)
BUSY BUSY BUSY BUSY
Access Time to Address Disable Time to Address Access Time to Chip Select Disable Time to Chip Deselect
-- -- -- -- -- -- 5 -- 0 25 -- 0 0 -- --
30 25 25 25 55 40 --
NOTE 9
-- -- -- -- -- -- 5 -- 0 25 -- 0 0 -- --
35 30 30 25 60 45 --
NOTE 9
-- -- -- -- -- -- 5 -- 0 25 -- 0 0 -- --
35 30 30 25 65 50 --
NOTE 9
-- -- -- -- -- -- 5 -- 0 25 -- 0 0 -- --
35 30 30 25 70 55 --
NOTE 9
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2795 tbl 10
Write Pulse to Data Delay Write Data Valid to Read Data Delay Arbitration Priority Set-Up Time
BUSY
Disable to Valid Time
(4)
Busy Cycle-Slave Mode
Write to BUSY Input Write Hold after BUSY Write Pulse to Data Delay Address Set-Up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time
-- -- 55 -- -- 25 25
-- -- 60 -- -- 30 30
-- -- 65 -- -- 32 32
-- -- 70 -- -- 35 35
tWDD tAS tWR tINS tINR
Interrupt Timing
NOTES: 1. This parameter is guaranteed by design but not tested. 2. To access RAM, CS VIL and SEM VIH. To access semaphore, CS VIH and SEM VIL. 3. When the module is being used in the Master Mode (M/S VIH). 4. When the module is being used in the Slave Mode (M/S VIL). 5. Port-to-Port delay through the RAM cells from the writing port to the reading port. 6. To ensure that the earlier of the two ports wins. 7. To ensure that the write cycle is inhibited during contention. 8. To ensure that a write cycle is completed after contention. 9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tWP (actual).
7.02
5
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1, 2, 4)
tRC ADDRESS tAA DATAOUT PREVIOUS DATA VALID tOH DATA VALID tOH
2795 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (1, 3, 5)
tSOP tACE
CS
tSOP tAOE tCHZ (6)
OE
tOLZ DATAOUT tCLZ ICC CURRENT ISB tPU
(6)
2795 drw 06
(6)
tOHZ
(6)
DATA VALID
(6)
tPD
(6)
50%
50%
NOTES: 1. R/W is HIGH for Read Cycles 2. Device is continuously enabled CS VIL. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition LOW. 4. OE VIL 5. To access RAM, CS VIL and SEM VIH. To access semaphore, CS VIH and SEM VIL. 6. This parameter is guaranteed by design but not tested.
7.02
6
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1, 2, 4) W
tWC ADDRESS tCHZ
(9)
OE
tAW
CS
tAS R/ W tWHZ DATAOUT
(4) (9) (6)
tWP
(2)
tWR
(7)
t OW
(9) (4)
tDW DATAIN
tDH DATA VALID
2795 drw 07
CS TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 4)
tWC ADDRESS tAW
CS
t AS R/ W tDW DATAIN tDH DATA VALID
2795 drw 08
(6)
tWP
(2)
tWR
(7)
NOTES: 1. R/W must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW R/W. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must be applied. 5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
7.02
7
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE(1)
tAW A0-A2 VALID ADDRESS tWP tWR tAA VALID ADDRESS tSOP tACE tOH
SEM
tDW DATA0 tAS R/ tWP DATAIN VALID tDH DATAOUT VALID
W
tSWRD tAOE
OE
tSOP WRITE CYCLE
NOTE: 1. CS VIH for the duration of the above timing (both write and read cycle).
READ CYCLE
2795 drw 09
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4)
A0A -- A2A MATCH
SIDE
(2)
"A"
R/ WA
SEMA
tSPS A0B -- A2B MATCH
(2)
SIDE
"B"
R/ WB
SEMB
2795 drw 10
NOTES: 1. DOR = DOL VIL, (L_ CS = R_ CS) VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. "A" may be either left or right port. "B" is the opposite port from "A". 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.02
8
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (M/S VIH)(2) S
tWC ADDR R MATCH tWP R/W R tDW DATAIN R tAPS ADDR L
(1)
tDH
VALID tBDA MATCH tBDD
BUSY
L
tDDD DATAOUT L tWDD
NOTES: 1. To ensure that the earlier of the two ports wins. 2. (L_ CS = R_ CS) VIL 3. OE VIL for the reading port.
(3)
VALID
2795 drw 11
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (M/S VIH)(1, 2) S
tWC ADDR R MATCH tWP R/W R tDW DATAIN R VALID tDH
ADDR L
MATCH tDDD
DATAOUT L tWDD
NOTES: 1. BUSY input equals HIGH for the writing port. 2. (L_ CS = R_ CS) VIL
VALID
2795 drw 12
7.02
9
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (M/S VIL) S
tWP R/W tWB tWH DATAINR
2795 drw 13
BUSY
TIMING WAVEFORM OF BUSY ARBITRATION (CS CONTROLLED TIMING)(1) CS
ADDR "A" AND "B" ADDRESS MATCH
CS
"A" tAPS
(2)
tBDC
CS
"B" tBAC
BUSY
"B"
2795 drw 14
TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDR "A" tAPS ADDR"B"
(2)
ADDRESS "N"
MATCHING ADDRESS "N" tBAA tBDA
BUSY
"B"
2795 drw 15
NOTES: 1. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 2. If tAPS is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
7.02
10
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT CYCLE(1)
tWC ADDR "A" tAS
CE
INTERRUPT SET ADDRESS
(3)
(2)
tWR
(4)
"A"
R/W 1"A" tINS
INT
(3)
"B"
2795 drw 16
tRC ADDR "B" tAS
CE
INTERRUPT CLEAR ADDRESS
(3)
(2)
"B"
OE
"B" tINR (3)
INT
"B"
2795 drw 17
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 2. See Interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLE I: Non-Contention Read/Write Control(1)
Inputs Outputs Mode Description Deselected or Power Down Write Read Outputs Disabled
2795 tbl 13
CS
H L L X
R/W X L H X
OE
X X L H
SEM
H H H X
I/O High-Z Data_In Data_OUT High-Z
NOTE: 1. The conditions for non-contention are L_A (0-13) R_A (0-13). 2. denotes a LOW to HIGH waveform transition.
TRUTH TABLE II: Semaphore Read/Write Control
Inputs(2) Outputs Mode Description Read Data in Semaphore Flag Write Data_IN (0, 8, 16, 24) Not Allowed
2795 tbl 14
CS
H H L
R/W W H X
OE
L X X
SEM
L L L
I/O Data_OUT Data_IN --
7.02
11
IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INTERRUPT/BUSY FLAGS, DEPTH & WIDTH EXPANSION, MASTER/SLAVE CONTROL, SEMAPHORES
For more details regarding Interrupt/Busy flags, depth and/or width expansion, master/slave control, or semaphore operations, please consult the IDT7006 data sheet.
PACKAGE DIMENSIONS
1.325 1.355 0.025 0.060 0.125 0.200 0.100 BSC 0.016 0.020 0.040 0.060 0.175 MAX.
1.325 1.355 0.235 MAX.
TOP VIEW 1.200 BSC
1.200 BSC
BOTTOM VIEW Pin A1
2795 drw 18
ORDERING INFORMATION
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
BLANK B
Commercial (0C to +70C) Military (-55C to +125C)Semiconductor Components compliant to MIL-STD-883, Class B Ceramic PGA (Pin Grid Array) (Commercial Only) (Commercial Only) (Military Only) (Military Only)
G 30 35 40 45
Speed in Nanoseconds
S
Standard Power
7M1002
16K x 32 CMOS Dual-Port Static RAM Module
2795 drw 19
7.02
12

▲Up To Search▲

Price & Availability of IDT7M1002

	To Download IDT7M1002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .